1. FIELD OF THE INVENTION
This invention relates to a single chip cache memory and, more specifically, to the architectural arrangement therefore to provide easy cascading and testing.
2. DESCRIPTION OF THE PRIOR ART
A cache memory is temporary storage device of small capacity relative to the main storage of a computer which is rapidly accessible and is normally positioned between the central processing unit (CPU) and the main memory. In conventional cache memory circuits, an SRAM is provided with, for example, 2K.times.8 storage locations. The memory includes address and data input lines, a chip select circuit, a read circuit and a write circuit. In this manner, data is written into or read from the addressed memory location when the appropriate chip select signal and read or write signal is provided. The prior art cache memory has no provision for comparison, parity generation, parity checking or reset.
An improved type of circuit is a cache address comparator of the type found in, for example the TMS 2150 cache address comparator produced by Texas Instruments Incorporated. This cache address comparator does not contain a read function, thereby limiting the operations which it is capable of performing or which can be performed therein. Such prior art cache memories include an SRAM, parity generator and checker, comparator and reset circuit. These prior art comparators do not contain a read function. In addition, the comparators are difficult to cascade because they utilize NMOS totem-pole and can not be ANDed with other similar circuits without the addition of a great deal of additional circuitry. This limits the ability to increase memory storage capability or to increase the range of addresses to which they may be capable of response. It is readily apparent that these deficiencies of the prior art severely limit the use of such cache address comparators.
It is therefore desireable to improve the cache memory or comparator capability relating to storage capacity as well as to address capability relating to storage capacity as well as to address responsiveness. In addition, the prior art cache memories and comparators are difficult to test on-line. It is desirable that such memories be capable of rapid testing, on line, on a periodic basis, to insure proper operation thereof.